1. Field of the Invention
The present invention relates generally to integrated circuit memory devices comprising an array of memory locations and further comprising multiple ports for receiving multiple combinations of binary address signals to simultaneously address multiple locations of the array and more particularly to integrated circuit memory devices including means for controlling a simultaneous provision of a combination of binary address signals to more than one port.
2. Description of the Related Art
There is a trend in computer technology today toward the use of multi-processors which increase the speed and throughput of computational tasks by distributing such tasks between more than one processing unit. An important aspect of typical multi-processor systems is the sharing of memory space by multiple processing units of the system. One earlier system, for example, provided access to shared memory space on a serial basis such that only one processing unit could access the space at any given time. More recently, however, dual-port memory devices have been developed which permit less restricted access to shared memory space by more than one processing unit.
Referring to the illustrative block diagram of FIG. 1, for example, there is shown a multiprocessor system 18 comprising a dual port memory device 20 and two respective microprocessors 22 and 24. The memory device 20 includes a left port for receiving left port binary address signals at terminals labelled A0L-A9L and left port binary input/output data signals at terminals labelled D0L-D7L. It also includes a right port for receiving right port binary address signals at terminals labelled A0R-A9R and right port binary input/output data signals labelled D0R-D7R. The left port receives address and data signals from the first microprocessor 22, and the right port receives address and data signals from the second microprocessor 24. The memory array 20 further includes respective left and right status signal terminals labelled respectively BUSYL and BUSYR which are discussed further below.
Typical earlier memory arrays of the general type illustrated in FIG. 1 included contention logic circuitry (not shown) used to arbitrate access to a respective memory location when more than one microprocessor simultaneously sought access to that location. For example, the contention logic circuitry often compared the combinations of address signals provided to the respective left and right address terminals A0L-A9L and A0R-A9R in order to determine whether there was a simultaneous attempt to access a single memory location of the memory array 20. In the event that simultaneous access was sought, the contention logic circuitry would determine which of the microprocessors 22 or 24 seeking to access the memory location would be provided first access to the location. The circuitry then provided, on a respective left or right status signal terminal, an active status signal, to a microprocessor whose access was to be delayed. A microprocessor granted first access then proceeded with its task; while a microprocessor whose access was delayed, for example, awaited access.
While these earlier multiple port integrated circuit memory array devices generally have been acceptable, there have been shortcomings with their use. More specifically, situations often arise in which an active status signal is prematurely provided to a microprocessor such that its access to a memory location is delayed even though there actually is no need for such a delay. For example, with regard to the system 18 of FIG. 1, the first microprocessor 22 might momentarily provide to the left port address terminals A0L-A9L a combination of binary address signals corresponding to a first location and then provide a combination of address signals corresponding to a second location. Simultaneously with the provision of address signals to the left address terminals which correspond to the first location, the second microprocessor 24 might provide to the right port address terminals A0R-A09 a combination of binary address signals which correspond to a third location, and then after a short period of time may provide a combination of address signals which correspond to the first location (where the first, second and third locations are distinct). Although there may be no period of time when both the first and second microprocessors 22 and 24 simultaneously provide combinations of address signals corresponding to the first location, an active status signal erroneously may be provided to either one or the other of the microprocessors 22 or 24 and incorrectly indicate a temporary match in address signal combinations.
Furthermore, problems may arise due to very brief matches in address signal combinations provided to the respective right and left address terminals as a result of address signal skew. Address signal skew can result when signals comprising a combination of signals provided to the left port, for example, change logical states at slightly different points in time. For example, in changing from a combination of address signals corresponding to one location to a combination corresponding to another location, it may be necessary to change the logical states of both the signals provided to terminal A0R and to terminal A9R. However, the signal provided to A0R, for example, might not change its logical state until five nanoseconds after the signal provided to A9R has changed its logical state. The five nanosecond delay would represent address signal skew which sometimes can result in a temporary match in combinations of address signals provided to the respective left and right ports, and consequently, may result in the provision of an active status signal which unnecessarily can delay access to the memory array 20 by one of the microprocessors 22 or 24.
Therefore, there has been a need for an integrated circuit device including a multiple port memory array which is more tolerant to near matches and to very brief temporary matches in combinations of binary address signals provided to more than one port such that access to the memory array by a microprocessor is not unnecessarily delayed. The present invention meets this need.